12 lines
267 B
Systemverilog
12 lines
267 B
Systemverilog
`timescale 1ps/1ps
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module __@TOPMODULE@__;
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logic clock = 1'b0;
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initial forever #(5ns) clock = ~clock;
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@TOPMODULE@ @TOPMODULE@ (clock);
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initial begin
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$dumpfile("@WORKDIR@/@TOPMODULE@.vcd");
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$dumpvars(0, @TOPMODULE@);
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end
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endmodule
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