hny-2026/README.md

HNY2026 - New Year's Greeting on FPGA

A Chisel-based FPGA design that transmits a New Year's greeting message via LED patterns on a TangNano 1K development board.

How It Works

The greeting is encoded as:

• Green LED = bit '0'
• Red LED = bit '1'
• 8-bit ASCII (LSB) + parity bit + empty bit

FPGA Workflow (TangNano 1K)

Full build and load to FPGA SRAM:

mill tangNano1k.load

Full build and burn FPGA flash:

mill tangNano1k.burn

Step-by-step:

mill tangNano1k.generate   # Generate SystemVerilog
mill tangNano1k.synth      # Synthesize with Yosys
mill tangNano1k.pnr        # Place and route with Nextpnr
mill tangNano1k.bitstream  # Generate bitstream
mill tangNano1k.load       # Load to FPGA SRAM
mill tangNano1k.burn       # Burn to FPGA flash

Run all unit tests:

mill hny2026.test

Requirements

• Scala and Mill
• Yosys with Slang plugin
• Nextpnr
• Gowin pack tool (from Apicula package)
• openFPGALoader
• TangNano 1K development board (GW1NZ-LV1QN48C6/I5)

Yosys and other utilities can be taken from the OSS CAD Suite package or installed using the package manager Nix:

nix-shell shell.nix

Decoding the Message

Capture the LED blinking on video (30 fps recommended), then extract the bit pattern: green=0, red=1.