Add VCS and Xcelium run time. Fix RTL for VCS to work correctly

test-vcs/.dir-locals.el

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+((verilog-mode . ((flycheck-verilator-include-path . ("../source")))))

test-vcs/__build.sh

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+#!/usr/bin/env bash
+set -e
+
+. ../scripts/sim_vars.sh
+
+rm -rf csrc simv.daidir simv
+
+vcs -full64 -lca -sverilog -notice -nc -timescale=1ns/1ps -f $FFILE -pvalue+top.CPU_COUNT=$CPU_COUNT -l build.log top.sv

test-vcs/__run.sh

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+#!/usr/bin/env bash
+
+. ../scripts/sim_vars.sh
+
+./simv +dlen=$BLOCK_SIZE

test-vcs/top.sv

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+`timescale 1ps/1ps
+
+module top #(parameter CPU_COUNT = 1024);
+    logic clock = 1'b0;
+    initial forever #(10ns/2) clock = ~clock;
+    testbench #(CPU_COUNT) testbench (clock);
+endmodule