Add old (without --timing) verilator test

This commit is contained in:
Nikolay Puzanov
2024-10-02 17:25:04 +03:00
parent 8b8f63105c
commit c277e3482a
17 changed files with 70 additions and 28 deletions

1
test-verilator5/.gitignore vendored Normal file
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top

19
test-verilator5/Makefile Normal file
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TOP_MODULE = top
SOURCES = top.sv
FLAGS_FILE = ../source/sources.f
INCLUDES =
PARAMS :=
THREADS := 1
FLAGS = -Wno-WIDTH --top-module $(TOP_MODULE) +1800-2017ext+sv \
--timing --Mdir $(TOP_MODULE) -o $(TOP_MODULE) -f $(FLAGS_FILE) \
$(PARAMS) --timescale "1ps/1ps" --threads $(THREADS) -j 0
# FLAGS += --trace
all: $(SOURCES)
verilator $(FLAGS) --binary $(INCLUDES) $(SOURCES)
clean:
rm -rf $(TOP_MODULE)

7
test-verilator5/__build.sh Executable file
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#!/usr/bin/env bash
set -e
. ../scripts/sim_vars.sh
make clean
make OPT_FAST="-Os -march=native" VM_PARALLEL_BUILDS=0 PARAMS="-GCPU_COUNT=$CPU_COUNT" THREADS=$THREADS

5
test-verilator5/__run.sh Executable file
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#!/usr/bin/env bash
. ../scripts/sim_vars.sh
./top/top +dlen=$BLOCK_SIZE

7
test-verilator5/top.sv Normal file
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`timescale 1ps/1ps
module top #(parameter CPU_COUNT = 2);
logic clock = 1'b0;
initial forever #(10ns/2) clock = ~clock;
testbench #(CPU_COUNT) testbench (clock);
endmodule