Add VCS version number

README.md

@@ -40,33 +40,40 @@
 
 ## Результаты для 1024 процессоров
 
-- Xeon E5-2630v3 @ 2.40GHz
+- 2 x Xeon E5-2630v3 @ 2.40GHz (no HT), 64GB RAM
-- Verilator 5.011 devel rev v5.010-98-g15f8ebc56
+- NixOS 24.11 Linux Kernel 6.6.67
+
+- GCC 13.3.0
+- Verilator 5.028 2024-08-21 rev v5.028
 - Icarus Verilog 13.0 (devel) (s20221226-127-gdeeac2edf)
-- ModelSim SE-64 2020.4 (Revision: 2020.10)
 - QuestaSim 64 2021.1 (Revision: 2021.1)
 - Vivado 2021.1
+- [OSS CVC](https://github.com/cambridgehackers/open-src-cvc) (rev. 782c69a)
+- VCS T-2022.06
 
 Время выполнения бенчмарка на блоке 1кБ (чч:мм:сс):
 ```
 | Симулятор             | Build    | Run      |
 +-----------------------+----------+----------+
-| Icarus Verilog        | 00:00:27 | 19:04:37 |
+| CVC                   | 00:00:05 | 00:57:15 |
-| ModelSim              | 00:00:00 | 01:33:14 |
+| Icarus Verilog        | 00:00:23 | 16:15:02 |
-| QuestaSim             | 00:00:00 | 01:29:38 |
+| QuestaSim (+acc)      | 00:00:00 | 01:06:54 |
-| VCS                   | TBD      |          |
+| QuestaSim (-O5)       | 00:00:00 | 00:06:50 |
-| Verilator (1 thread)  | 00:12:03 | 00:02:57 |
+| VCS                   | 00:00:25 | 00:04:12 |
-| Verilator (8 threads) | 00:18:45 | 00:01:33 |
+| Verilator (1 thread)  | 00:09:23 | 00:02:45 |
-| XSIM                  | 00:00:29 | 02:08:54 |
+| Verilator (8 threads) | 00:09:02 | 00:00:50 |
+| XSIM                  | 00:00:29 | 02:06:16 |
 | Xcelium               | TBD      |          |
 ```
 
-Удалось протестировать Xcelium и VCS на другом оборудованиии и привести время
+Удалось протестировать Xcelium на другом оборудованиии и привести время выполнения
-выполнения бенчмарка к остальным симам. Время сборки на этих симуляторах примерно
+бенчмарка к остальным симам. Время сборки на этих симуляторах примерно соответствует
-соответствует времени сборки на XSIM (Xcelium ближе к Modelsim).
+времени сборки на XSIM.
 
 В таблице ниже показано относительное время выполнения теста, приведенное к времени
-выполнения на многопоточном Вериляторе.
+выполнения на многопоточном Вериляторе. Вериляторы 5.028 и 4.120 показали практически
+одинаковую скорость, разность в пределах погрешности. Но в 5.028 была включена опция
+`--timing`, а клок формировался в верилоге.
 
 "По просьбе выживших, имена были изменены. Из уважения к погибшим, остальное было
 рассказано в точности так, как это произошло."
@@ -74,12 +81,13 @@
 ```
 | Симулятор             | Run  |
 +-----------------------+------+
-| Icarus Verilog        |  738 |
+| CVC                   |   69 |
-| ModelSim              |   60 |
+| Icarus Verilog        | 1170 |
-| QuestaSim             |   58 |
+| QuestaSim (+acc)      |   80 |
-| VCS                   |  3.8 |
+| QuestaSim (-O5)       |  8.2 |
-| Verilator (1 thread)  |  1.9 |
+| VCS                   |  5.0 |
+| Verilator (1 thread)  |  3.3 |
 | Verilator (8 threads) |    1 |
-| XSIM                  |   83 |
+| XSIM                  |  152 |
-| Xcelium               |    4 |
+| Xcelium               |   ~4 |
 ```

source/md5calculator.sv

@@ -216,9 +216,7 @@ module md5calculator
        );
 
     // Print console output
-    initial
+    always @(posedge clock) begin
-      forever begin
-          @(posedge clock);
         if (!reset && console_send) begin
             $write("%c", o_console_data);
             $fflush;

source/testbench.sv

@@ -9,10 +9,11 @@ module testbench #(parameter CPU_COUNT = 1024)
     logic [31:0] data_len;
     logic [CPU_COUNT-1:0] done_all;
 
-    for (genvar ncpu = 0; ncpu < CPU_COUNT; ncpu = ncpu + 1) begin : cpus
+    int cycle = 0;
-        localparam logic [31:0] MD5IN = ncpu;
+    always @(posedge clock) cycle <= cycle + 1;
 
-        logic done;
+    for (genvar ncpu = 0; ncpu < CPU_COUNT; ncpu = ncpu + 1) begin : cpus
+        logic done, done_ack = 1'b0;
         logic reset;
         logic [127:0] md5;
 
@@ -32,27 +33,27 @@ module testbench #(parameter CPU_COUNT = 1024)
           if(!$value$plusargs("dlen=%d", data_len))
             data_len = DATA_LEN;
 
-        initial begin
+        int reset_duration;
-            reset = 1'b1;
+        initial reset_duration = $urandom % CPU_COUNT + 2;
-            repeat($urandom % 5 + 2) @(posedge clock);
+        assign reset = cycle <= reset_duration;
-            reset = 1'b0;
-            @(posedge clock);
 
-            while(!done) @(posedge clock);
+        always @(posedge clock) begin
-            $display("MD5(0x%x) = %x", MD5IN, md5);
+            if (cycle > reset_duration && done && !done_ack) begin
+                done_ack <= 1'b1;
+                $display("MD5(0x%x) = %x", ncpu, md5);
+            end
         end
     end
 
     // Wait for complete
-    initial begin
+    always @(posedge clock) begin
-        $display("--- BENCH BEGIN ---");
+        if (cycle == 0) $display("--- BENCH BEGIN ---");
-
+        else if (cycle > 5) begin
-        repeat(5) @(posedge clock);
+            if (&done_all) begin
-        while ((&done_all) == 1'b0) @(posedge clock);
-        @(posedge clock);
-
                 $display("--- BENCH DONE ---");
                 $finish;
             end
+        end
+    end
 
 endmodule // testbench

test-cvc/.dir-locals.el

@@ -0,0 +1 @@
+((verilog-mode . ((flycheck-verilator-include-path . ("../source")))))

test-cvc/.gitignore

@@ -0,0 +1,6 @@
+top
+picorv32_tcm.sv
+simbench-all.v
+testbench.sv
+top-mod.sv
+verilog.log

test-cvc/__build.sh

@@ -0,0 +1,25 @@
+#!/usr/bin/env bash
+set -e
+
+. ../scripts/sim_vars.sh
+
+rm -rf ./top
+
+# CVC do not have $urandom function
+cp ../source/testbench.sv ./
+patch testbench.sv testbench.patch
+
+# CVC bug with nonblocking assignment to part of vector
+cp ../source/picorv32_tcm.sv ./
+patch picorv32_tcm.sv picorv32_tcm.patch
+
+# CVC does not support setting parameter via command line
+cp ./top.sv ./top-mod.sv
+sed -i -e "s/CPU_COUNT = 1024/CPU_COUNT = $CPU_COUNT/" top-mod.sv
+
+sources=$(cat $FFILE | grep -v "testbench.sv\|picorv32_tcm.sv")
+
+sv2v --top=top -w simbench-all.v top-mod.sv testbench.sv picorv32_tcm.sv $sources
+patch simbench-all.v simbench-all.patch
+
+cvc64 -o top -O -pipe +large +nospecify simbench-all.v

test-cvc/__run.sh

@@ -0,0 +1,5 @@
+#!/usr/bin/env bash
+
+. ../scripts/sim_vars.sh
+
+./top +dlen=$BLOCK_SIZE

test-cvc/picorv32_tcm.patch

@@ -0,0 +1,18 @@
+diff --git a/source/picorv32_tcm.sv b/source/picorv32_tcm.sv
+index 29e4d6c..763adc7 100644
+--- a/source/picorv32_tcm.sv
++++ b/source/picorv32_tcm.sv
+@@ -39,9 +39,12 @@ module picorv32_tcm #(parameter ADDR_WIDTH = 8,
+     assign word_addr = byte_addr[ADDR_WIDTH-1:2];
+ 
+     always @(posedge clock) begin
++        logic [31:0] tmp;
++        tmp = ram[word_addr];
+         for (int n = 0; n < 4; n += 1)
+           if (write && mem_wstrb[n])
+-            ram[word_addr][n*8 +: 8] <= mem_wdata[n*8 +: 8];
++            tmp[n*8 +: 8] = mem_wdata[n*8 +: 8];
++        ram[word_addr] <= tmp;
+ 
+         mem_rdata <= ram[word_addr];
+     end

test-cvc/shell.nix

@@ -0,0 +1,4 @@
+{ pkgs ? import <nixpkgs> {} }:
+
+with pkgs;
+mkShell { packages = [ gnumake zlib /* haskellPackages.sv2v */ ]; }

test-cvc/simbench-all.patch

@@ -0,0 +1,20 @@
+--- simbench-all.v	2025-01-08 22:09:06.737402979 +0300
++++ simbench-all.v1	2025-01-08 22:08:27.142909974 +0300
+@@ -1,3 +1,4 @@
++`timescale 1ps/1ps
+ module top;
+ 	parameter CPU_COUNT = 1024;
+ 	reg clock = 1'b0;
+@@ -13,10 +14,9 @@
+ 	wire [CPU_COUNT - 1:0] done_all;
+ 	reg signed [31:0] cycle = 0;
+ 	always @(posedge clock) cycle <= cycle + 1;
+-	genvar _gv_ncpu_1;
++	genvar ncpu;
+ 	generate
+-		for (_gv_ncpu_1 = 0; _gv_ncpu_1 < CPU_COUNT; _gv_ncpu_1 = _gv_ncpu_1 + 1) begin : cpus
+-			localparam ncpu = _gv_ncpu_1;
++		for (ncpu = 0; ncpu < CPU_COUNT; ncpu = ncpu + 1) begin : cpus
+ 			wire done;
+ 			reg done_ack = 1'b0;
+ 			wire reset;

test-cvc/testbench.patch

@@ -0,0 +1,13 @@
+diff --git a/source/testbench.sv b/source/testbench.sv
+index 2949591..084d7a3 100644
+--- a/source/testbench.sv
++++ b/source/testbench.sv
+@@ -34,7 +34,7 @@ module testbench #(parameter CPU_COUNT = 1024)
+             data_len = DATA_LEN;
+ 
+         int reset_duration;
+-        initial reset_duration = $urandom % CPU_COUNT + 2;
++        initial reset_duration = $unsigned($random) % CPU_COUNT + 2;
+         assign reset = cycle <= reset_duration;
+ 
+         always @(posedge clock) begin

test-cvc/top.sv

@@ -0,0 +1,7 @@
+`timescale 1ps/1ps
+
+module top #(parameter CPU_COUNT = 1024);
+    logic clock = 1'b0;
+    initial forever #5000 clock = ~clock;
+    testbench #(CPU_COUNT) testbench (clock);
+endmodule

test-modelsim-O5/.dir-locals.el

@@ -0,0 +1 @@
+((verilog-mode . ((flycheck-verilator-include-path . ("../source")))))

test-modelsim-O5/.gitignore

@@ -0,0 +1,2 @@
+testbench
+transcript

test-modelsim-O5/__build.sh

@@ -0,0 +1,7 @@
+#!/usr/bin/env bash
+set -e
+
+. ../scripts/sim_vars.sh
+
+rm -rf testbench
+vlog -sv -work testbench -vopt $param -f $FFILE top.sv

test-modelsim-O5/__run.sh

@@ -0,0 +1,5 @@
+#!/usr/bin/env bash
+
+. ../scripts/sim_vars.sh
+
+vsim -batch -voptargs=-O5 -do "run -all" -quiet +dlen=$BLOCK_SIZE -GCPU_COUNT=$CPU_COUNT -lib testbench top

test-modelsim-O5/top.sv

@@ -0,0 +1,7 @@
+`timescale 1ps/1ps
+
+module top #(parameter CPU_COUNT = 1024);
+    logic clock = 1'b0;
+    initial forever #(10ns/2) clock = ~clock;
+    testbench #(CPU_COUNT) testbench (clock);
+endmodule

test-modelsim/__run.sh

@@ -2,4 +2,4 @@
 
 . ../scripts/sim_vars.sh
 
-vsim -batch -voptargs=+acc=npr -do "run -all" -quiet +dlen=$BLOCK_SIZE -GCPU_COUNT=$CPU_COUNT -lib testbench top
+vsim -batch -voptargs="+acc" -do "run -all" -quiet +dlen=$BLOCK_SIZE -GCPU_COUNT=$CPU_COUNT -lib testbench top

test-verilator4/Makefile

@@ -7,8 +7,8 @@ PARAMS :=
 THREADS := 1
 
 FLAGS = -Wno-WIDTH -cc --top-module $(TOP_MODULE) +1800-2017ext+sv \
-	--timing --Mdir $(TOP_MODULE) -o $(TOP_MODULE) -f $(FLAGS_FILE) \
+	--Mdir $(TOP_MODULE) -o $(TOP_MODULE) -f $(FLAGS_FILE) \
-	$(PARAMS) --timescale "1ps/1ps" --threads $(THREADS) -j 0
+	$(PARAMS) --timescale "1ps/1ps" --threads $(THREADS) -j 16
 
 # FLAGS += --trace
 

test-verilator5/.gitignore

@@ -0,0 +1 @@
+top

test-verilator5/Makefile

@@ -0,0 +1,19 @@
+TOP_MODULE = top
+
+SOURCES = top.sv
+FLAGS_FILE = ../source/sources.f
+INCLUDES =
+PARAMS :=
+THREADS := 1
+
+FLAGS = -Wno-WIDTH --top-module $(TOP_MODULE) +1800-2017ext+sv \
+	--timing --Mdir $(TOP_MODULE) -o $(TOP_MODULE) -f $(FLAGS_FILE) \
+	$(PARAMS) --timescale "1ps/1ps" --threads $(THREADS) -j 0
+
+# FLAGS += --trace
+
+all: $(SOURCES)
+	verilator $(FLAGS) --binary $(INCLUDES) $(SOURCES)
+
+clean:
+	rm -rf $(TOP_MODULE)

test-verilator5/__build.sh

@@ -0,0 +1,7 @@
+#!/usr/bin/env bash
+set -e
+
+. ../scripts/sim_vars.sh
+
+make clean
+make OPT_FAST="-Os -march=native" VM_PARALLEL_BUILDS=0 PARAMS="-GCPU_COUNT=$CPU_COUNT" THREADS=$THREADS

test-verilator5/__run.sh

@@ -0,0 +1,5 @@
+#!/usr/bin/env bash
+
+. ../scripts/sim_vars.sh
+
+./top/top +dlen=$BLOCK_SIZE

test-verilator5/top.sv

@@ -0,0 +1,7 @@
+`timescale 1ps/1ps
+
+module top #(parameter CPU_COUNT = 2);
+    logic clock = 1'b0;
+    initial forever #(10ns/2) clock = ~clock;
+    testbench #(CPU_COUNT) testbench (clock);
+endmodule