60 lines
1.5 KiB
Systemverilog
60 lines
1.5 KiB
Systemverilog
`timescale 1ps/1ps
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module testbench #(parameter CPU_COUNT = 1024)
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(input clock);
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localparam DATA_ADDR = 32'h00010000;
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localparam DATA_LEN = 1024;
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logic [31:0] data_len;
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logic [CPU_COUNT-1:0] done_all;
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int cycle = 0;
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always @(posedge clock) cycle <= cycle + 1;
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for (genvar ncpu = 0; ncpu < CPU_COUNT; ncpu = ncpu + 1) begin : cpus
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logic done, done_ack = 1'b0;
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logic reset;
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logic [127:0] md5;
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assign done_all[ncpu] = done;
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md5calculator cpu
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(.clock, .reset, .done,
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.md5_data_addr(DATA_ADDR),
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.md5_data_len(data_len),
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.md5(md5));
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initial
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for (int n = 0; n < (2 ** (cpu.rom.ADDR_WIDTH-2)); n += 1)
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cpu.rom.ram[n] = ncpu;
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initial
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if(!$value$plusargs("dlen=%d", data_len))
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data_len = DATA_LEN;
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int reset_duration;
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initial reset_duration = $urandom % CPU_COUNT + 2;
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assign reset = cycle <= reset_duration;
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always @(posedge clock) begin
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if (cycle > reset_duration && done && !done_ack) begin
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done_ack <= 1'b1;
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$display("MD5(0x%x) = %x", ncpu, md5);
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end
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end
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end
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// Wait for complete
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always @(posedge clock) begin
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if (cycle == 0) $display("--- BENCH BEGIN ---");
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else if (cycle > 5) begin
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if (&done_all) begin
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$display("--- BENCH DONE ---");
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$finish;
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end
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end
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end
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endmodule // testbench
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