Refactor: rename verilog-align-ports-* to verilog-align-*

README.md

@@ -1,20 +1,20 @@
-# verilog-align-ports
+# verilog-align
 
-Align SystemVerilog ANSI-style port declarations in a contiguous block around point.
+Align SystemVerilog port declarations, instantiations, and signal declarations around point.
 
 ## Features
 
 - Aligns direction, type, range, name, and trailing `//` comments.
 - Works on the contiguous block of port declarations above and below point.
 - Stops at the first non-port line (including blank lines).
-- Aligns named port connections in module instantiations via `verilog-align-ports-instantiation`.
-- Aligns signal declarations via `verilog-align-ports-declarations`.
+- Aligns named port connections in module instantiations via `verilog-align-instantiation`.
+- Aligns signal declarations via `verilog-align-declarations`.
 
 ## Installation
 
 ```elisp
-(add-to-list 'load-path "/path/to/verilog-align-ports")
-(require 'verilog-align-ports)
+(add-to-list 'load-path "/path/to/verilog-align")
+(require 'verilog-align)
 ```
 
 ## Usage
@@ -25,12 +25,12 @@ Align SystemVerilog ANSI-style port declarations in a contiguous block around po
 For module instantiations:
 
 1. Place point on a named port connection line (e.g., `.clk_i (clk)` or `.full_o,`).
-2. Run `M-x verilog-align-ports-instantiation`.
+2. Run `M-x verilog-align-instantiation`.
 
 For signal declarations:
 
 1. Place point on a declaration line (e.g., `logic foo;` or `wire [3:0] bar;`).
-2. Run `M-x verilog-align-ports-declarations`.
+2. Run `M-x verilog-align-declarations`.
 
 Example input: