Refactor: rename verilog-align-ports-* to verilog-align-*
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207
verilog-align-test.el
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207
verilog-align-test.el
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;;; verilog-align-test.el --- Tests for verilog-align -*- lexical-binding: t; -*-
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;;; Commentary:
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;; ERT tests for verilog-align.
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;;; Code:
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(require 'ert)
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(defconst verilog-align-test--dir
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(file-name-directory (or load-file-name buffer-file-name)))
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(load-file (expand-file-name "verilog-align.el"
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verilog-align-test--dir))
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(ert-deftest verilog-align-ports-aligns-block ()
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(let* ((input (concat
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(mapconcat
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#'identity
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'("module fifo_sync #("
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" parameter integer FifoWriteDepth = 2048,"
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" parameter integer DataWidth = 32,"
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" parameter integer WrDataCountWidth = $clog2(FifoWriteDepth)+1,"
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" parameter integer RdDataCountWidth = 4"
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") ("
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" input wire rst_i, // rst,"
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" input wire clk_i, // wr_clk,"
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" input wire wr_en_i, // wr_en,"
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" input wire [DataWidth-1:0] d_i, // din,"
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" output logic full_o, // full,"
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" output logic [WrDataCountWidth-1:0] wr_data_count_o, // wr_data_count,"
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" input wire rd_en_i, // rd_en,"
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" output [DataWidth-1:0] d_o, // dout,"
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" output empty_o,// empty,"
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" output logic valid_o // data_valid"
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");")
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"\n")
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"\n"))
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(expected (concat
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(mapconcat
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#'identity
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'("module fifo_sync #("
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" parameter integer FifoWriteDepth = 2048,"
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" parameter integer DataWidth = 32,"
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" parameter integer WrDataCountWidth = $clog2(FifoWriteDepth)+1,"
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" parameter integer RdDataCountWidth = 4"
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") ("
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" input wire rst_i, // rst,"
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" input wire clk_i, // wr_clk,"
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" input wire wr_en_i, // wr_en,"
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" input wire [DataWidth-1:0] d_i, // din,"
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" output logic full_o, // full,"
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" output logic [WrDataCountWidth-1:0] wr_data_count_o, // wr_data_count,"
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" input wire rd_en_i, // rd_en,"
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" output [DataWidth-1:0] d_o, // dout,"
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" output empty_o, // empty,"
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" output logic valid_o // data_valid"
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");")
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"\n")
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"\n")))
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(with-temp-buffer
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(insert input)
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(goto-char (point-min))
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(search-forward "input wire clk_i")
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(beginning-of-line)
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(verilog-align-ports)
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(should (string= (buffer-string) expected)))))
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(ert-deftest verilog-align-instantiation-aligns-block ()
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(let* ((input (concat
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(mapconcat
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#'identity
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'("fifo_sync #("
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" .FifoWriteDepth(FifoWriteDepth),"
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" .DataWidth(DataWidth),"
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" .DataCountWidth(WrDataCountW),"
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" .RdDataCountWidth(RdDataCountW)"
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") dut ("
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" .rst_i (rst), //rst"
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" .clk_i (clk),"
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" .wr_en_i (wr_en_i),"
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" .d_i (d_i), // di"
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" .full_o, // full"
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" .data_count_o (wr_data_count_o),"
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" .rd_en_i (rd_en_i),"
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" .d_o () , // do"
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" .empty_o , // empty"
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" .valid_o (valid_o)"
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");")
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"\n")
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"\n"))
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(expected (concat
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(mapconcat
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#'identity
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(list
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"fifo_sync #("
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" .FifoWriteDepth(FifoWriteDepth),"
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" .DataWidth(DataWidth),"
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" .DataCountWidth(WrDataCountW),"
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" .RdDataCountWidth(RdDataCountW)"
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") dut ("
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(concat " .rst_i" (make-string 8 ?\s) "(rst),"
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(make-string 13 ?\s) "//rst")
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(concat " .clk_i" (make-string 8 ?\s) "(clk),")
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(concat " .wr_en_i" (make-string 6 ?\s) "(wr_en_i),")
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(concat " .d_i" (make-string 10 ?\s) "(d_i),"
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(make-string 13 ?\s) "// di")
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(concat " .full_o," (make-string 25 ?\s) "// full")
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(concat " .data_count_o" (make-string 1 ?\s)
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"(wr_data_count_o),")
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(concat " .rd_en_i" (make-string 6 ?\s) "(rd_en_i),")
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(concat " .d_o" (make-string 10 ?\s) "(),"
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(make-string 16 ?\s) "// do")
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(concat " .empty_o," (make-string 24 ?\s) "// empty")
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(concat " .valid_o" (make-string 6 ?\s) "(valid_o)")
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");")
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"\n")
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"\n")))
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(with-temp-buffer
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(insert input)
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(goto-char (point-min))
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(search-forward ".clk_i")
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(beginning-of-line)
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(should (verilog-align-instantiation))
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(should (string= (buffer-string) expected)))))
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(ert-deftest verilog-align-instantiation-returns-nil-outside ()
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(with-temp-buffer
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(insert (concat
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(mapconcat
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#'identity
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'("fifo_sync #() dut ("
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" .rst_i (rst),"
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" .clk_i (clk)"
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");")
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"\n")
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"\n"))
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(goto-char (point-min))
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(search-forward "dut (")
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(beginning-of-line)
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(should (not (verilog-align-instantiation)))))
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(ert-deftest verilog-align-declarations-aligns-block ()
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(let* ((input (concat
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(mapconcat
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#'identity
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'("logic wr_en_i; // write enable"
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"logic [DataWidth-1:0] d_i; // data input"
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"logic full_o;"
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"logic [WrDataCountW-1:0] wr_data_count_o; // data count"
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"wire rd_en_i; // read enable"
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"logic [DataWidth-1:0] d_o;"
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"reg empty_o;// empty flag"
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"logic valid_o;")
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"\n")
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"\n"))
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(expected (concat
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(mapconcat
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#'identity
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(list
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(concat "logic" (make-string 20 ?\s)
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"wr_en_i;" (make-string 9 ?\s)
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"// write enable")
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(concat "logic" " " "[DataWidth-1:0]" (make-string 4 ?\s)
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"d_i;" (make-string 13 ?\s)
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"// data input")
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(concat "logic" (make-string 20 ?\s) "full_o;")
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(concat "logic" " " "[WrDataCountW-1:0]" " "
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"wr_data_count_o;" " " "// data count")
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(concat "wire" (make-string 21 ?\s)
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"rd_en_i;" (make-string 9 ?\s)
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"// read enable")
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(concat "logic" " " "[DataWidth-1:0]" (make-string 4 ?\s)
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"d_o;")
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(concat "reg" (make-string 22 ?\s)
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"empty_o;" (make-string 9 ?\s)
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"// empty flag")
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(concat "logic" (make-string 20 ?\s) "valid_o;")
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)
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"\n")
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"\n")))
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(with-temp-buffer
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(insert input)
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(goto-char (point-min))
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(search-forward "logic full_o")
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(beginning-of-line)
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(should (verilog-align-declarations))
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(should (string= (buffer-string) expected)))))
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(ert-deftest verilog-align-declarations-returns-nil-outside ()
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(with-temp-buffer
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(insert (concat
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(mapconcat
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#'identity
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'("module foo;"
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"logic a;"
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"endmodule")
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"\n")
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"\n"))
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(goto-char (point-min))
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(search-forward "module foo")
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(beginning-of-line)
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(should (not (verilog-align-declarations)))))
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(provide 'verilog-align-test)
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;;; verilog-align-test.el ends here
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