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Verilator: Generate correct reset

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This commit is contained in:
Nikolay Puzanov 2022-11-21 20:57:43 +03:00
parent 09781bd1b7
commit 838bbac645
1 changed files with 7 additions and 2 deletions
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9
_template_verilator/top.cpp
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@ -30,7 +30,10 @@ int main(int argc, char **argv)
clk->next_event();
/* Initial */
top->reset = 0;
top->reset = 1;
/* Cycle counter */
uint64_t cycle = 0;
/* ---- Evaluation loop ---- */
while (!ctx->gotFinish()) {
@ -47,13 +50,15 @@ int main(int argc, char **argv)
/* Put input values (after clock edge)*/
if (clk->is_posegde(top->clock)) {
top->reset = !top->reset;
top->reset = (cycle < 5) ? 1 : 0;
}
/* Trace steady-state values */
#if (VM_TRACE == 1)
if (vcd) vcd->dump(ctx->time());
#endif
cycle ++;
}
top->final();