np/verilog-playground
1
0
Fork 0
Code Issues 1 Pull Requests Projects Releases Wiki Activity

Top module for all simulators must have an input clock signal

Browse Source
This commit is contained in:
Nikolay Puzanov 2022-12-09 10:21:40 +03:00
parent 2f9f5b6dd1
commit cc605cce85
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
_web_server/server/playground-server.scm
View File

@ -794,7 +794,7 @@
"Rules:"
"0. Don't fool around ;)"
"1. The top module must be named 'testbench'."
"2. The top module for the Verilator must have an input clock signal."
"2. The top module must have an input clock signal."
"3. Code size should not exceed 10000 characters."
"4. Code execution time no longer than 5 seconds.")
"\\n"))))))