2023-06-02 11:08:51 +03:00

21 lines
386 B
Systemverilog

`timescale 1ps/1ps
/* verilator lint_off DECLFILENAME */
/* verilator lint_off MULTITOP */
/* verilator lint_off STMTDLY */
/* verilator lint_off INFINITELOOP */
/* verilator lint_off INITIALDLY */
module testbench;
initial begin
$finish;
end
`ifdef DUMP
initial begin
$dumpfile("testbench.fst");
$dumpvars(0, testbench);
end
`endif
endmodule