Nikolay Puzanov fce7e03306 Set output file name to module top

2022-11-17 13:24:30 +03:00

_template_iverilog

Initial commit

2022-11-17 13:02:15 +03:00

_template_verilator

Set output file name to module top

2022-11-17 13:24:30 +03:00

.gitignore

Initial commit

2022-11-17 13:02:15 +03:00

Description

Templates for quick simulate Verilog code

386 KiB

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