66 lines
1.7 KiB
Markdown
66 lines
1.7 KiB
Markdown
# verilog-align
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Align SystemVerilog port declarations, instantiations, and signal declarations around point.
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## Features
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- Aligns direction, type, range, name, and trailing `//` comments.
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- Works on the contiguous block of port declarations above and below point.
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- Stops at the first non-port line (including blank lines).
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- Aligns named port connections in module instantiations via `verilog-align-instantiation`.
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- Aligns signal declarations via `verilog-align-declarations`.
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## Installation
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```elisp
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(add-to-list 'load-path "/path/to/verilog-align")
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(require 'verilog-align)
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```
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## Usage
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1. Place point on a line that declares a port (input/output/inout).
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2. Run `M-x verilog-align-ports`.
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For module instantiations:
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1. Place point on a named port connection line (e.g., `.clk_i (clk)` or `.full_o,`).
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2. Run `M-x verilog-align-instantiation`.
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For signal declarations:
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1. Place point on a declaration line (e.g., `logic foo;` or `wire [3:0] bar;`).
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2. Run `M-x verilog-align-declarations`.
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Example input:
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```systemverilog
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input wire rst_i, // rst,
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input wire clk_i, // wr_clk,
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input wire [DataWidth-1:0] d_i, // din,
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output logic full_o, // full,
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output [DataWidth-1:0] d_o, // dout,
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output empty_o,// empty,
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output logic valid_o // data_valid
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```
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Example output:
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```systemverilog
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input wire rst_i, // rst,
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input wire clk_i, // wr_clk,
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input wire [DataWidth-1:0] d_i, // din,
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output logic full_o, // full,
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output [DataWidth-1:0] d_o, // dout,
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output empty_o, // empty,
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output logic valid_o // data_valid
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```
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## Tests
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Run:
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```bash
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./run-tests.sh
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```
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