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Top module for all simulators must have an input clock signal

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Nikolay Puzanov 2022-12-09 10:21:40 +03:00
parent 2f9f5b6dd1
commit cc605cce85
1 changed files with 1 additions and 1 deletions
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_web_server/server/playground-server.scm
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@ -794,7 +794,7 @@
"Rules:" "Rules:"
"0. Don't fool around ;)" "0. Don't fool around ;)"
"1. The top module must be named 'testbench'." "1. The top module must be named 'testbench'."
"2. The top module for the Verilator must have an input clock signal." "2. The top module must have an input clock signal."
"3. Code size should not exceed 10000 characters." "3. Code size should not exceed 10000 characters."
"4. Code execution time no longer than 5 seconds.") "4. Code execution time no longer than 5 seconds.")
"\\n")))))) "\\n"))))))