Nikolay Puzanov 90905544d4 Upcase signal values

2022-12-07 17:53:17 +03:00

_template_iverilog

Initial commit

2022-11-17 13:02:15 +03:00

_template_verilator

Verilator: Generate correct reset

2022-11-21 20:57:43 +03:00

_web_server

Upcase signal values

2022-12-07 17:53:17 +03:00

.gitignore

Fix gitignore

2022-11-29 20:55:24 +03:00

Description

Templates for quick simulate Verilog code

386 KiB

Languages

Scheme 70.5%

C++ 9.9%

HTML 8.9%

Dockerfile 3.1%

Shell 2.5%

Other 5.1%