Nikolay Puzanov np
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  • Joined on 2021-01-06
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np pushed to master at np/uprintf 2025-01-30 12:33:13 +03:00
782b91da67 Speed up printing of ^2 base
np pushed to master at np/uprintf 2025-01-28 11:07:59 +03:00
ee27e84544 Translated by DeepSeek :)
np pushed to master at np/uprintf 2025-01-28 10:53:36 +03:00
2417d2068e Add UPRINTF_CUSTOM_DIV_FUNC to Makefile
a3c69113f4 Add custom div functions
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np pushed to main at np/simbench 2025-01-10 11:01:57 +03:00
eac0c922c9 Add VCS version number
np pushed to main at np/simbench 2025-01-09 12:58:39 +03:00
2821d98c6b Add -O5 option to QuestaSim. Rerun benchmarks.
np pushed to main at np/simbench 2024-10-02 17:25:46 +03:00
c277e3482a Add old (without --timing) verilator test
np pushed to main at np/verilog-playground 2024-08-11 23:21:59 +03:00
3aee2d2f38 Fix help message
b84ec9a1c5 Remove clock from testbench input
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np pushed to main at np/embddr-scheme-library 2024-08-11 23:20:47 +03:00
3ccd9d2d22 Fix title absent
np pushed to main at np/embddr-scheme-library 2024-08-11 23:20:18 +03:00
53408f7bdf Exact numbers is not supported by gnuplot. Fix it
1487382015 Initial add gnuplot plotting
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np pushed to main at np/verilog-playground 2023-11-07 14:27:23 +03:00
1e0bfb58cf Add support for verilator 5.018+
np pushed to main at np/simbench 2023-07-11 19:46:55 +03:00
8b8f63105c Add CVC simulator run scripts
a71258f7f6 Remove unused localparam
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np pushed to main at np/simbench 2023-06-21 11:40:53 +03:00
575fc1cdca Remove relative build time from final results table
np pushed to main at np/simbench 2023-06-21 11:32:13 +03:00
31ac4a8d46 Add VCS and Xcelium run time. Fix RTL for VCS to work correctly
np pushed to main at np/verilog-playground 2023-06-02 11:09:42 +03:00
e67558de14 Enable dump in iverilog testbench template
np pushed to main at np/random-phrase-generator 2023-02-22 10:54:05 +03:00
256ee6269c Disable upcase converting
np pushed to main at np/random-phrase-generator 2023-02-20 16:21:06 +03:00
8251bc5b16 Rename script
np pushed to main at np/embddr-scheme-library 2023-02-20 15:16:16 +03:00
dfff93795e Add TODO
np pushed to main at np/verilog-playground 2022-12-13 11:49:35 +03:00
54f7e2be54 Enable trace of structs
np pushed to main at np/verilog-playground 2022-12-09 10:22:13 +03:00
cc605cce85 Top module for all simulators must have an input clock signal
np pushed to main at np/verilog-playground 2022-12-09 10:15:03 +03:00
2f9f5b6dd1 Disable Save hotkey (to prevent thoughtless use)