Nikolay Puzanov

np pushed to main at np/verilog-playground

2023-11-07 14:27:23 +03:00

1e0bfb58cf Add support for verilator 5.018+

np pushed to main at np/simbench

2023-07-11 19:46:55 +03:00

8b8f63105c Add CVC simulator run scripts

a71258f7f6 Remove unused localparam

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np pushed to main at np/simbench

2023-06-21 11:40:53 +03:00

575fc1cdca Remove relative build time from final results table

np pushed to main at np/simbench

2023-06-21 11:32:13 +03:00

31ac4a8d46 Add VCS and Xcelium run time. Fix RTL for VCS to work correctly

np pushed to main at np/verilog-playground

2023-06-02 11:09:42 +03:00

e67558de14 Enable dump in iverilog testbench template

np pushed to main at np/random-phrase-generator

2023-02-22 10:54:05 +03:00

256ee6269c Disable upcase converting

np pushed to main at np/random-phrase-generator

2023-02-20 16:21:06 +03:00

8251bc5b16 Rename script

np pushed to main at np/embddr-scheme-library

2023-02-20 15:16:16 +03:00

dfff93795e Add TODO

np pushed to main at np/verilog-playground

2022-12-13 11:49:35 +03:00

54f7e2be54 Enable trace of structs

np pushed to main at np/verilog-playground

2022-12-09 10:22:13 +03:00

cc605cce85 Top module for all simulators must have an input clock signal

np pushed to main at np/verilog-playground

2022-12-09 10:15:03 +03:00

2f9f5b6dd1 Disable Save hotkey (to prevent thoughtless use)

np pushed to main at np/verilog-playground

2022-12-09 09:23:16 +03:00

cb8bc37dfe Disable ligatures

np pushed to main at np/verilog-playground

2022-12-09 09:21:16 +03:00

1e12d5d3e2 Don't save unmodified code

np pushed to main at np/verilog-playground

2022-12-09 09:09:30 +03:00

1bc6ec544d Save code only by Save button. Save always to new location

np pushed to main at np/verilog-playground

2022-12-08 19:06:56 +03:00

d04282e1c7 Add simple scroll of long waveform

np opened issue np/verilog-playground#1

2022-12-07 18:30:03 +03:00

Веб-сервер работает в однопоточном режиме. Нужно добавить многопоточность

np pushed to main at np/verilog-playground

2022-12-07 18:08:17 +03:00

664b7b1f5c Buttons can move to new line

np pushed to main at np/verilog-playground

2022-12-07 17:55:33 +03:00

37b7a54d3b Visual improvements

01c982fada Fix parsing canvas width

931f4d8aa4 Fix signals sorting (put clock on the top)

90905544d4 Upcase signal values

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np pushed to main at np/verilog-playground

2022-12-07 17:01:12 +03:00

ab5db7f6e8 Add waveforms

np pushed to main at np/embddr-scheme-library

2022-12-07 12:51:41 +03:00

f9f22f4f31 Add optional signal filter predicate

7a88f6a05f Fix bug

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