Logo
Explore Help
Sign In
np/verilog-align-ports
1
0
Fork 0
You've already forked verilog-align-ports
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
4 Commits 1 Branch 0 Tags
508ebdc8e641dbf8b1897fbb968ea75ed3579917
Commit Graph

3 Commits

Author SHA1 Message Date
Nikolay Puzanov
508ebdc8e6 Add function for alignment of signal declarations. 2026-02-08 13:47:42 +03:00
Nikolay Puzanov
2102adc1da Add function for alignment of named port connections in module instantiations. 2026-02-08 13:39:22 +03:00
Nikolay Puzanov
a1107b911a Initial commit 2026-02-05 14:53:00 +03:00
Powered by Gitea Version: 1.25.4 Page: 23ms Template: 4ms
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API