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74e76d8131 |
@@ -10,4 +10,11 @@ module testbench;
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initial begin
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$finish;
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end
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`ifdef DUMP
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initial begin
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$dumpfile("testbench.fst");
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$dumpvars(0, testbench);
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end
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`endif
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endmodule
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@@ -3,10 +3,24 @@ FROM ubuntu:22.10
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LABEL description="Verilog playground"
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# Prepare OS
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RUN sed -i 's/^# *deb-src/deb-src/g' /etc/apt/sources.list
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RUN apt-get -y update \
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&& apt-get -y install iverilog guile-3.0 locales git
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&& apt-get -y install guile-3.0 locales git
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RUN sed -i '/en_US.UTF-8/s/^# //g' /etc/locale.gen \
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&& locale-gen
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RUN apt-get build-dep -y iverilog verilator
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# Build latest Icarus Veriolog
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WORKDIR /build
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RUN git clone --depth 1 https://github.com/steveicarus/iverilog.git
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WORKDIR /build/iverilog
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RUN sh ./autoconf.sh && ./configure --prefix=/usr && make -j2 && make install
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# Build latest Verilator
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WORKDIR /build
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RUN git clone --depth 1 https://github.com/verilator/verilator.git
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WORKDIR /build/verilator
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RUN autoconf && ./configure --prefix=/usr && make -j2 && make install
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# Environment
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ENV GIT_SSL_NO_VERIFY=1
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@@ -28,8 +42,10 @@ CMD [ "guile", "-e", "main", \
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"--port=8080", \
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"--addr=0.0.0.0", \
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"--host=https://play.embddr.com", \
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"--iverilog-exe=./iverilog", \
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"--vvp-exe=./vvp", \
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"--iverilog-wrap=./restrict", \
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"--vvp-wrap=./restrict", \
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"--verilator-sim-wrap=./restrict", \
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"--verilator-build-jobs=2", \
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"--max-len=10000", \
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"--work-base=play-work", \
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"--stor-base=/verilog-playground-store", \
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@@ -11,19 +11,25 @@
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box-sizing: border-box;
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margin: 0;
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padding: 0;
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font-variant-ligatures: none;
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}
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body {
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padding: 3px;
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font-size: 14px;
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font-family: 'JetBrains Mono', monospace;
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font-size: 10pt;
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}
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pre {
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font-family: 'JetBrains Mono', monospace;
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font-size: 10pt;
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}
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#buttons {
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color: white;
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background-color: #2d3d40;
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width: 100%;
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height: 38px;
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padding: 4px;
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padding: 3px;
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font-size: inherit;
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}
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@@ -38,16 +44,13 @@
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background-color: #dbdbdb;
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margin-left: 1px;
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margin-right: 1px;
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height: 100%;
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margin-top: 2px;
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margin-bottom: 2px;
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height: 25px;
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}
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button span.text { padding: 4px; }
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#text {
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font-family: 'JetBrains Mono', monospace;
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font-size: inherit;
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}
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#editor {
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height: 75vh;
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width: 100%;
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@@ -63,6 +66,40 @@
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overflow: scroll;
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}
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svg {
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fill: none;
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stroke: white;
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stroke-width: 0;
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shape-rendering: crispEdges;
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}
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svg text {
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font-family: 'JetBrains Mono', monospace;
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font-size: 10pt;
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fill: white;
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}
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svg #wave-signals {
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stroke: #00fcff;
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stroke-width: 1;
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}
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svg #wave-clock {
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stroke: #fffe9a;
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font-size: 8pt;
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stroke-width: 1;
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}
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svg #wave-signals text { font-size: 8pt; }
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svg #wave-clock text { font-size: 8pt; }
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svg #wave-delim {
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stroke: #d0d0d0;
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stroke-width: 2;
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}
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svg #wave-background { fill: #1e2426; }
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@media (orientation: landscape) and (not (pointer: coarse)) {
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body {
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display: flex;
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@@ -84,7 +121,7 @@
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height: 100%;
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}
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#log {
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#logdiv pre {
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position: absolute;
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height: 100%;
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}
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@@ -95,21 +132,18 @@
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<body>
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<div id="buttons">
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<button onclick="show_help()"><span class="text">?</span></button>
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<button onclick="save_code('%SAVECODEURI%')"><span class="text">Save (ctrl-s)</span></button>
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<button onclick="save_code('%SAVEASURI%')"><span class="text">Save as new</span></button>
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<button onclick="save_code('%SAVECODEURI%')"><span class="text">Save</span></button>
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Sim:
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<button onclick="send_to_sim('%IVERILOGPOSTURI%')"><span class="text">Icarus</span></button>
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<button onclick="send_to_sim('%VERILATORPOSTURI%')"><span class="text">Verilator</span></button>
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<!-- button><span class="text">Verilator</span></button -->
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</div>
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<div id="text">
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<div id="editor">@CODE@</div>
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<div id="logdiv">
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<pre id="log"></pre>
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</div>
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||||
<div id="logdiv"></div>
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||||
</div>
|
||||
|
||||
|
||||
<script src="https://cdnjs.cloudflare.com/ajax/libs/ace/1.13.1/ace.js" type="text/javascript" charset="utf-8"></script>
|
||||
<script src="https://cdnjs.cloudflare.com/ajax/libs/ace/1.13.1/ext-language_tools.js" type="text/javascript" charset="utf-8"></script>
|
||||
<script type="text/javascript" charset="utf-8">
|
||||
@@ -123,10 +157,11 @@
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enableBasicAutocompletion : true,
|
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enableLiveAutocompletion : true
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});
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const log_area = document.getElementById('log');
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const log_area = document.getElementById('logdiv');
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function send_to_sim(uri) {
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query = uri + "?width=" + log_area.clientWidth;
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log_area.innerHTML = "Please wait...";
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fetch(uri,
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fetch(query,
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{
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method: 'POST',
|
||||
headers: {
|
||||
@@ -157,13 +192,6 @@
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alert("%HELPSTRING%");
|
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};
|
||||
|
||||
document.addEventListener('keydown', (e) => {
|
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if (e.key.toLowerCase() === 's' && e.ctrlKey) {
|
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e.preventDefault();
|
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save_code();
|
||||
}
|
||||
});
|
||||
|
||||
</script>
|
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</body>
|
||||
</html>
|
||||
|
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@@ -19,7 +19,8 @@
|
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(ice-9 popen))
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|
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(import (embddr common)
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(embddr optargs))
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(embddr optargs)
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(embddr vcd))
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|
||||
(define INDEX-FILE "index.html")
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(define DELETE-WORK-DIR #t)
|
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@@ -28,15 +29,15 @@
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||||
(define SNIPPET-FILE "code.sv")
|
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(define IVERILOG-METATOP-FILE "top_iverilog.sv")
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||||
(define VERILATOR-CPP-FILE "top_verilator.cpp")
|
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(define USE-TIME-IN-SAVE-URL #f)
|
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|
||||
(define IVERILOG-EXE "iverilog")
|
||||
(define VVP-EXE "vvp")
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(define VERILATR-EXE "verilator")
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(define VERILATOR-EXE "verilator")
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|
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(define URI-IVERILOG "iverilog")
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(define URI-VERILATOR "verilator")
|
||||
(define URI-SAVE-CODE "save")
|
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(define URI-SAVEAS-CODE "saveas")
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||||
|
||||
(define LOG-DBG 3)
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(define LOG-VERBOSE 2)
|
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@@ -48,13 +49,20 @@
|
||||
(define DEFAULT-CODE
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||||
(string-append
|
||||
"`timescale 1ps/1ps\n\n"
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(format "module ~a (input clock);\n" TOP-MODULE)
|
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;; (format "module ~a (input clock);\n" TOP-MODULE)
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(format "module ~a;\n" TOP-MODULE)
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" logic clock = 1'b0;\n"
|
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" initial forever #(5ns) clock = ~clock;\n"
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"\n"
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||||
" initial begin\n"
|
||||
" $display(\"Hello world!\");\n"
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" repeat(10) @(posedge clock);\n"
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" $finish();\n"
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||||
" end\n"
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||||
"endmodule\n"))
|
||||
|
||||
(define DEFAULT-CANVAS-WIDTH 800)
|
||||
|
||||
(define (multistring . strings)
|
||||
(apply string-append
|
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(insert-between strings "\n")))
|
||||
@@ -77,7 +85,7 @@
|
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;;; Logger
|
||||
;;;
|
||||
(define (logger . args)
|
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(when (not (null? args))
|
||||
(unless (null? args)
|
||||
(let ((prefix
|
||||
(format "~a | "
|
||||
(strftime "%c" (localtime (current-time))))))
|
||||
@@ -178,7 +186,7 @@
|
||||
(when (or (not max-file-size)
|
||||
(< readed max-file-size))
|
||||
(let ((data (get-bytevector-n in max-read-length)))
|
||||
(when (not (eof-object? data))
|
||||
(unless (eof-object? data)
|
||||
(put-bytevector port data)
|
||||
(loop (+ readed (bytevector-length data))))))))
|
||||
#:binary #t))))
|
||||
@@ -195,6 +203,246 @@
|
||||
#:content-type content-type
|
||||
#:content-type-params content-type-params))
|
||||
|
||||
;;;
|
||||
;;; Simple format with convert input number to inexact numbers
|
||||
;;;
|
||||
(define (format-inex . args)
|
||||
(apply format
|
||||
(map (lambda (arg)
|
||||
(if (number? arg)
|
||||
(exact->inexact
|
||||
(/ (round (* arg 100)) 100))
|
||||
arg))
|
||||
args)))
|
||||
|
||||
;;;
|
||||
;;; Make SVG drawing of VCD signals
|
||||
;;;
|
||||
(define* (vcd-signal->svg signal tstart tend x y width height text-position
|
||||
#:key (id #f) (data-hw 3))
|
||||
(let* ((time-per-pixel (/ (- tend tstart) width))
|
||||
(sig-width (vcd-signal-size signal))
|
||||
(sig-type (vcd-signal-type signal))
|
||||
(y0 y)
|
||||
(y1 (+ y height))
|
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(yz (+ y (/ height 2)))
|
||||
(half-dy (/ (- y1 y0) 2))
|
||||
(id (if id (format " id=\"~a\"" id) "")))
|
||||
|
||||
(let next-sample ((samples (vcd-signal-get signal))
|
||||
(value (if (eq? sig-type 'real)
|
||||
0
|
||||
(make-string sig-width #\x)))
|
||||
(time tstart)
|
||||
(svg '()))
|
||||
|
||||
(if (null? samples)
|
||||
svg
|
||||
(let ((sample-time (car (car samples)))
|
||||
(sample-value (cdr (car samples))))
|
||||
(if (and (< sample-time tend)
|
||||
(or (< (- sample-time time) time-per-pixel)
|
||||
(and (equal? value sample-value)
|
||||
(not (eq? sig-type 'event)))))
|
||||
(next-sample
|
||||
(cdr samples)
|
||||
(if (<= sample-time tstart)
|
||||
sample-value
|
||||
value)
|
||||
time svg)
|
||||
(next-sample
|
||||
(cdr samples) sample-value sample-time
|
||||
(cons
|
||||
(cond
|
||||
((or (eq? sig-type 'bits)
|
||||
(eq? sig-type 'real))
|
||||
|
||||
(if (and (= sig-width 1)
|
||||
(not (eq? sig-type 'real))
|
||||
(not (char-ci=? (string-ref value 0) #\x)))
|
||||
;; Scalar
|
||||
(let ((x0 (+ x (/ (- time tstart) time-per-pixel)))
|
||||
(x1 (+ x (/ (- sample-time tstart) time-per-pixel))))
|
||||
(string-append
|
||||
(format-inex "<path~a d=\"M~a ~a v~a\"/>" id x0 y0 (- y1 y0))
|
||||
(format-inex "<path~a d=\"M~a ~a h~a\"/>"
|
||||
id x0
|
||||
(cond
|
||||
((equal? value "0") y1)
|
||||
((equal? value "1") y0)
|
||||
(else yz))
|
||||
(- x1 x0))))
|
||||
|
||||
;; Vector or Real
|
||||
(let ((x0 (+ x (/ (- time tstart) time-per-pixel)))
|
||||
(x1 (+ x (/ (- sample-time tstart) time-per-pixel))))
|
||||
(string-append
|
||||
;; Horizontal lines
|
||||
(let ((x0 (+ x0 (if (<= time tstart) 0 data-hw)))
|
||||
(x1 (- x1 (if (>= sample-time tend) 0 data-hw))))
|
||||
(format-inex
|
||||
"<path~a d=\"M~a ~a L~a ~a M~a ~a L~a ~a\"/>"
|
||||
id x0 y0 x1 y0 x0 y1 x1 y1))
|
||||
|
||||
;; Left cross
|
||||
(if (<= time tstart)
|
||||
""
|
||||
(format-inex "<path~a d=\"M~a ~a l~a ~a\"/><path d=\"M~a ~a l~a ~a\"/>"
|
||||
id
|
||||
x0 yz data-hw (- half-dy)
|
||||
x0 yz data-hw (+ half-dy)))
|
||||
|
||||
;; Right cross
|
||||
(if (>= sample-time tend)
|
||||
""
|
||||
(format-inex "<path~a d=\"M~a ~a l~a ~a\"/><path d=\"M~a ~a l~a ~a\"/>"
|
||||
id
|
||||
x1 yz (- data-hw) (- half-dy)
|
||||
x1 yz (- data-hw) (+ half-dy)))
|
||||
|
||||
;; Text
|
||||
(format-inex "<svg~a x=\"~a\" y=\"~a\" width=\"~a\" height=\"~a\">"
|
||||
id
|
||||
(+ x0 data-hw)
|
||||
y0
|
||||
(- x1 x0 (* data-hw 2))
|
||||
(- y1 y0))
|
||||
(format-inex "<text x=\"~a\" y=\"~a\">" 0 text-position)
|
||||
(string-upcase
|
||||
(if (or (eq? sig-type 'real)
|
||||
(<= sig-width 4))
|
||||
value
|
||||
(vcd-binary->hex value #t)))
|
||||
"</text></svg>"))))
|
||||
|
||||
;; Event TODO
|
||||
((eq? sig-type 'event)
|
||||
""))
|
||||
svg))))))))
|
||||
|
||||
;;;
|
||||
;;; Make legend SVG text for VCD
|
||||
;;;
|
||||
(define* (vcd-signals->legend signals text-spacing text-position)
|
||||
(if (null? signals)
|
||||
""
|
||||
(let ((common-scope-len
|
||||
(length
|
||||
(fold
|
||||
(lambda (scope common)
|
||||
(let loop ((scope scope)
|
||||
(common common)
|
||||
(out '()))
|
||||
(if (or (null? scope)
|
||||
(null? common))
|
||||
(reverse out)
|
||||
(if (string-ci= (car scope)
|
||||
(car common))
|
||||
(loop (cdr scope)
|
||||
(cdr common)
|
||||
(cons (car scope) out))
|
||||
(reverse out)))))
|
||||
(vcd-signal-scope (car signals))
|
||||
(map vcd-signal-scope (cdr signals))))))
|
||||
(map
|
||||
(lambda (sig n)
|
||||
(string-append
|
||||
(format-inex "<text x=\"0\" y=\"~a\">~a</text>"
|
||||
(+ (* n text-spacing) text-position)
|
||||
(string-concatenate
|
||||
(insert-between
|
||||
(append
|
||||
(drop (vcd-signal-scope sig)
|
||||
common-scope-len)
|
||||
`(,(vcd-signal-name sig)))
|
||||
".")))))
|
||||
signals
|
||||
(iota (length signals))))))
|
||||
|
||||
;;;
|
||||
;;; Create SVG from VCD
|
||||
;;;
|
||||
(define* (vcd->svg vcd width #:key
|
||||
(signal-height 15)
|
||||
(signal-text-position 12)
|
||||
(margin 5)
|
||||
(signal-spacing 5)
|
||||
(legend-width 150)
|
||||
(extra-delim-y 3))
|
||||
|
||||
(let ((tstart (apply min (vcd-timestamps vcd)))
|
||||
(tend (apply max (vcd-timestamps vcd)))
|
||||
(signals (sort
|
||||
(vcd-signals vcd)
|
||||
(lambda (a b)
|
||||
(and (not (equal? (vcd-signal-name b) "clock"))
|
||||
(or
|
||||
(and (equal? (vcd-signal-name a) "clock")
|
||||
(not (equal? (vcd-signal-name b) "clock")))
|
||||
|
||||
(< (length (vcd-signal-scope a))
|
||||
(length (vcd-signal-scope b)))
|
||||
|
||||
(string-ci<? (vcd-signal-name a)
|
||||
(vcd-signal-name b))))))))
|
||||
|
||||
(if (<= tend tstart)
|
||||
'()
|
||||
(let ((signals-x (+ (* 2 margin) legend-width))
|
||||
(signals-w (- width legend-width (* 3 margin)))
|
||||
(height
|
||||
(+ (* 2 margin)
|
||||
(* signal-height (length signals))
|
||||
(* signal-spacing (- (length signals) 1)))))
|
||||
|
||||
(append
|
||||
;; Header
|
||||
`(,(format-inex "<svg id=\"wave\" width=\"~a\" height=\"~a\"" width height)
|
||||
,(format "preserveAspectRatio=\"xMidYMin slice\" role=\"img\">")
|
||||
,(format "<g id=\"wave-background\"><rect width=\"100%\" height=\"100%\"/></g>"))
|
||||
|
||||
;; Legend
|
||||
`(,(format-inex "<svg id=\"wave-legend\" x=\"~a\" y=\"~a\" width=\"~a\" height=\"~a\">"
|
||||
margin margin legend-width (- height (* 2 margin))))
|
||||
(vcd-signals->legend signals
|
||||
(+ signal-height signal-spacing)
|
||||
signal-text-position)
|
||||
'("</svg>")
|
||||
|
||||
;; Clock
|
||||
`(,(format "<g id=\"wave-clock\">"))
|
||||
(vcd-signal->svg (car signals) tstart tend
|
||||
signals-x margin
|
||||
signals-w signal-height signal-text-position)
|
||||
'("</g>")
|
||||
|
||||
;; Rest
|
||||
`(,(format "<g id=\"wave-signals\">"))
|
||||
(fold
|
||||
(lambda (sig n out)
|
||||
(append
|
||||
out
|
||||
(vcd-signal->svg sig tstart tend
|
||||
signals-x
|
||||
(+ margin
|
||||
(* n signal-height)
|
||||
(* n signal-spacing))
|
||||
signals-w signal-height signal-text-position)))
|
||||
'()
|
||||
(cdr signals)
|
||||
(iota (length
|
||||
(cdr signals))
|
||||
1))
|
||||
'("</g>")
|
||||
|
||||
;; Delimiter
|
||||
`(,(format-inex "<g id=\"wave-delim\"><path d=\"M~a ~a v~a\"/></g>"
|
||||
(+ legend-width (* 2 margin)) (- margin extra-delim-y)
|
||||
(- height (* 2 (- margin extra-delim-y)))))
|
||||
|
||||
;; Close svg tag
|
||||
'("</svg>"))))))
|
||||
|
||||
;;;
|
||||
;;; Execute system command and capture stdout and stderr to string
|
||||
;;;
|
||||
@@ -205,6 +453,22 @@
|
||||
(out (get-string-all p)))
|
||||
(values (close-pipe p) out)))
|
||||
|
||||
;;;
|
||||
;;; Same as system-to-string but returns execution time (in ms) also
|
||||
;;;
|
||||
(define* (system-to-string-with-time cmd #:key (pwd #f))
|
||||
(let ((start-time (gettimeofday)))
|
||||
(let-values
|
||||
(((status out)
|
||||
(system-to-string cmd #:pwd pwd)))
|
||||
(let ((stop-time (gettimeofday)))
|
||||
(values status out
|
||||
(exact->inexact
|
||||
(- (+ (* (car stop-time) 1000)
|
||||
(/ (cdr stop-time) 1000))
|
||||
(+ (* (car start-time) 1000)
|
||||
(/ (cdr start-time) 1000)))))))))
|
||||
|
||||
;;;
|
||||
;;; Execute system command and capture stdout and stderr to string list
|
||||
;;;
|
||||
@@ -218,10 +482,10 @@
|
||||
;;;
|
||||
;;; Make pretty log from executable output
|
||||
;;;
|
||||
(define (exe-log-pretty cmdline status out)
|
||||
(define (exe-log-pretty cmdline status out time)
|
||||
(string-append
|
||||
(format "$ ~a\n" cmdline)
|
||||
(format "Return code: ~a\n" status)
|
||||
(format "Return code: ~a, Exec time: ~a ms\n" status time)
|
||||
(if (string-null? out)
|
||||
"\n"
|
||||
(format "--\n~a\n" out))))
|
||||
@@ -287,8 +551,8 @@
|
||||
|
||||
(with-output-to-file command-file
|
||||
(lambda ()
|
||||
(println "~a" verilog-file)
|
||||
(println "~a" metatop-file)
|
||||
(println "~a" verilog-file)
|
||||
(println "+define+TESTBENCH")
|
||||
(println "+timescale+1ps/1ps"))))
|
||||
work-dir))
|
||||
@@ -297,7 +561,7 @@
|
||||
;;; Create workdir for Verilator
|
||||
;;; Returns directory path
|
||||
;;;
|
||||
(define* (make-verilator-workdir code cpp base top)
|
||||
(define* (make-verilator-workdir code cpp jobs base top)
|
||||
(let-values (((work-dir verilog-file command-file)
|
||||
(make-sim-workdir code base top)))
|
||||
(let ((cpp-file (path+ work-dir (format "~a.cpp" top))))
|
||||
@@ -307,116 +571,145 @@
|
||||
|
||||
(with-output-to-file command-file
|
||||
(lambda ()
|
||||
(println "+define+TESTBENCH")
|
||||
(println "-DTESTBENCH")
|
||||
(println "--timescale 1ps/1ps")
|
||||
(println "--top-module ~a" top)
|
||||
(println "--Mdir ~a" (path+ work-dir top))
|
||||
(println "-cc")
|
||||
(println "-O2")
|
||||
(when (> jobs 0)
|
||||
(println "--build-jobs ~a" jobs))
|
||||
(println "-o ~a" top)
|
||||
(println "--exe")
|
||||
(println "--build")
|
||||
(println "-sv")
|
||||
(println "-Wno-WIDTH")
|
||||
(println "+1800-2017ext+sv")
|
||||
(println "+1800-2023ext+sv")
|
||||
(println "--timing")
|
||||
(println "--trace")
|
||||
(println "--trace-structs")
|
||||
(println "--trace-depth 1")
|
||||
(println "--quiet-exit")
|
||||
(println "~a" verilog-file)
|
||||
(println "~a.cpp" top))))
|
||||
work-dir))
|
||||
|
||||
;;;
|
||||
;;; Execute secuence of commands and return (values status "execution log")
|
||||
;;; Break execution on error
|
||||
;;;
|
||||
(define (exec-sequence cmds)
|
||||
(let-values
|
||||
(((status logs)
|
||||
(let next-cmd ((cmds cmds)
|
||||
(logs '()))
|
||||
(if (null? cmds)
|
||||
(values 0 logs)
|
||||
(let ((cmd (car cmds)))
|
||||
(let-values (((status out time)
|
||||
(system-to-string-with-time cmd)))
|
||||
(let ((logs (cons (exe-log-pretty cmd status out time) logs)))
|
||||
(if (zero? status)
|
||||
(next-cmd (cdr cmds) logs)
|
||||
(values status logs)))))))))
|
||||
(values status (string-concatenate (reverse logs)))))
|
||||
|
||||
;;;
|
||||
;;; Read and parse VCD file
|
||||
;;;
|
||||
(define* (vcd-file-read file #:optional (signal-need? (lambda (s) #t)))
|
||||
(if (file-exists? file)
|
||||
(guard #f
|
||||
(call-with-input-file file
|
||||
(cut vcd-parse <> signal-need?)))
|
||||
#f))
|
||||
|
||||
;;;
|
||||
;;; Compile sources and execute simulation with Icarus Verilog
|
||||
;;; Returns (values status log)
|
||||
;;; Returns (values status log vcd)
|
||||
;;;
|
||||
(define (exec-sim-iverilog top work-dir iverilog-wrap vvp-wrap)
|
||||
(let ((command-file (path+ work-dir (format "~a.vc" top)))
|
||||
(exe-file (path+ work-dir (format "~a.out" top))))
|
||||
;; Compile
|
||||
(let ((cmdline (format "~a -g2012 -s __~a__ -o ~a -c~a"
|
||||
(wrap-exe IVERILOG-EXE iverilog-wrap)
|
||||
top exe-file command-file)))
|
||||
(let-values (((status out)
|
||||
(system-to-string cmdline)))
|
||||
(let ((compile-log
|
||||
(exe-log-pretty cmdline status out)))
|
||||
(if (not (zero? status))
|
||||
(values status compile-log)
|
||||
(let* ((command-file (path+ work-dir (format "~a.vc" top)))
|
||||
(exe-file (path+ work-dir (format "~a.out" top)))
|
||||
(vcd-file (path+ work-dir (format "~a.vcd" top)))
|
||||
(cmds `(,(format "~a -g2012 -s __~a__ -o ~a -c~a"
|
||||
(wrap-exe IVERILOG-EXE iverilog-wrap)
|
||||
top exe-file command-file)
|
||||
,(format "~a -N ~a" (wrap-exe VVP-EXE vvp-wrap) exe-file))))
|
||||
|
||||
;; Execute
|
||||
(let ((cmdline (format "~a -N ~a" (wrap-exe VVP-EXE vvp-wrap) exe-file)))
|
||||
(let-values (((status out)
|
||||
(system-to-string cmdline)))
|
||||
(let ((execution-log
|
||||
(exe-log-pretty cmdline status out)))
|
||||
(values status (string-append compile-log execution-log)))))))))))
|
||||
(let-values (((status log)
|
||||
(exec-sequence cmds)))
|
||||
(if (zero? status)
|
||||
(values status log (vcd-file-read
|
||||
vcd-file
|
||||
(lambda (sig)
|
||||
(>= (length (vcd-signal-scope sig)) 2))))
|
||||
(values status log #f)))))
|
||||
|
||||
;;;
|
||||
;;; Compile sources and execute simulation with Verilator
|
||||
;;; Returns (values status log)
|
||||
;;; Returns (values status log vcd)
|
||||
;;;
|
||||
(define (exec-sim-verilator top work-dir verilator-wrap verilator-sim-wrap)
|
||||
;; Compile
|
||||
(let* ((command-file (path+ work-dir (format "~a.vc" top)))
|
||||
(cmdline (format "~a -f ~a"
|
||||
(wrap-exe VERILATR-EXE verilator-wrap)
|
||||
command-file)))
|
||||
(let-values (((status out)
|
||||
(system-to-string cmdline)))
|
||||
(let ((compile-log
|
||||
(exe-log-pretty cmdline status out)))
|
||||
(if (not (zero? status))
|
||||
(values status compile-log)
|
||||
(vcd-file (path+ work-dir (format "~a.vcd" top)))
|
||||
(cmds `(,(format "~a -f ~a"
|
||||
(wrap-exe VERILATOR-EXE verilator-wrap)
|
||||
command-file)
|
||||
,(wrap-exe (path+ work-dir (format "~a/~a" top top))
|
||||
verilator-sim-wrap))))
|
||||
|
||||
;; Execute
|
||||
(let ((cmdline (wrap-exe (path+ work-dir (format "~a/~a" top top))
|
||||
verilator-sim-wrap)))
|
||||
(let-values (((status out)
|
||||
(system-to-string cmdline)))
|
||||
(let ((execution-log
|
||||
(exe-log-pretty cmdline status out)))
|
||||
(values status (string-append compile-log execution-log))))))))))
|
||||
(let-values (((status log)
|
||||
(exec-sequence cmds)))
|
||||
(if (zero? status)
|
||||
(values status log (vcd-file-read
|
||||
vcd-file
|
||||
(lambda (sig)
|
||||
(>= (length (vcd-signal-scope sig)) 2))))
|
||||
(values status log #f)))))
|
||||
|
||||
;;;
|
||||
;;; Execute simulation
|
||||
;;;
|
||||
(define* (exec-sim simulator code base top #:key
|
||||
(vvp-wrap "") (iverilog-wrap "") (metatop "")
|
||||
(verilator-wrap "") (verilator-sim-wrap "") (verilator-cpp ""))
|
||||
(verilator-wrap "") (verilator-sim-wrap "")
|
||||
(verilator-cpp "") (verilator-build-jobs 0))
|
||||
(let-values
|
||||
(((work-dir status log)
|
||||
(((work-dir status log vcd)
|
||||
(cond
|
||||
;; Run Icarus Verilog
|
||||
((eq? simulator 'iverilog)
|
||||
(let ((work-dir (make-iverilog-workdir code metatop base top)))
|
||||
(let-values (((status log)
|
||||
(let-values (((status log vcd)
|
||||
(exec-sim-iverilog top work-dir iverilog-wrap vvp-wrap)))
|
||||
(values work-dir status log))))
|
||||
(values work-dir status log vcd))))
|
||||
|
||||
;; Run Verilator
|
||||
((eq? simulator 'verilator)
|
||||
(let ((work-dir (make-verilator-workdir code verilator-cpp base top)))
|
||||
(let-values (((status log)
|
||||
(let ((work-dir (make-verilator-workdir code verilator-cpp verilator-build-jobs base top)))
|
||||
(let-values (((status log vcd)
|
||||
(exec-sim-verilator top work-dir verilator-wrap verilator-sim-wrap)))
|
||||
(values work-dir status log))))
|
||||
(values work-dir status log vcd))))
|
||||
|
||||
;; Inknown simulator
|
||||
(else
|
||||
(values #f #f #f)))))
|
||||
(values #f #f #f #f)))))
|
||||
|
||||
(if (not work-dir)
|
||||
("ERROR: Unknown simulator")
|
||||
(values ("ERROR: Unknown simulator") #f)
|
||||
(begin
|
||||
;; Delete work dir
|
||||
(when DELETE-WORK-DIR
|
||||
(delete-recursive work-dir))
|
||||
|
||||
;; Return log
|
||||
(string-append
|
||||
log
|
||||
(format "-----------------\nSimulation complete~a\n"
|
||||
(if (zero? status) " succesfully"" with errors")))))))
|
||||
;; Return (values log vcd)
|
||||
(values
|
||||
(string-append
|
||||
log
|
||||
(format "-----------------\nSimulation complete~a\n"
|
||||
(if (zero? status) " succesfully"" with errors")))
|
||||
vcd)))))
|
||||
|
||||
;;;
|
||||
;;; Get app version
|
||||
@@ -434,7 +727,7 @@
|
||||
;;; Get storage dir from URI
|
||||
;;;
|
||||
(define (get-storage-dir uri root-path)
|
||||
(string-trim
|
||||
(string-trim-both
|
||||
(substring (uri-path uri)
|
||||
(string-length root-path))
|
||||
#\/))
|
||||
@@ -480,28 +773,47 @@
|
||||
(call-with-input-file (path+ path SNIPPET-FILE)
|
||||
get-string-all))
|
||||
|
||||
;;;
|
||||
;;; Make log HTML
|
||||
;;;
|
||||
(define* (make-log-html log vcd canvas-width #:key
|
||||
(minimum-sample-width 10)
|
||||
(maximum-canvas-width 20000))
|
||||
(if vcd
|
||||
(let ((need-width
|
||||
(* minimum-sample-width
|
||||
(length (vcd-timestamps vcd)))))
|
||||
(format "~a<br/>\n<pre id=\"log\">~a</pre>\n"
|
||||
(string-concatenate
|
||||
(vcd->svg vcd
|
||||
(if (< need-width canvas-width)
|
||||
canvas-width
|
||||
(if (> need-width maximum-canvas-width)
|
||||
maximum-canvas-width
|
||||
need-width))))
|
||||
log))
|
||||
(format "<pre>~a</pre>\n" log)))
|
||||
|
||||
;;;
|
||||
;;; Web page handler
|
||||
;;;
|
||||
(define (make-page-handler host root index-file
|
||||
work-base stor-base
|
||||
max-code-size
|
||||
max-code-size sanitize
|
||||
iverilog-wrap vvp-wrap
|
||||
verilator-wrap verilator-sim-wrap)
|
||||
verilator-wrap verilator-sim-wrap verilator-build-jobs)
|
||||
|
||||
(let* ((root-path (split-and-decode-uri-path root))
|
||||
(root (encode-and-join-uri-path root-path))
|
||||
(iverilog-path (append root-path `(,URI-IVERILOG)))
|
||||
(verilator-path (append root-path `(,URI-VERILATOR)))
|
||||
(savecode-path (append root-path `(,URI-SAVE-CODE)))
|
||||
(saveas-path (append root-path `(,URI-SAVEAS-CODE)))
|
||||
(index-html
|
||||
(read-template-text
|
||||
index-file
|
||||
`(("IVERILOGPOSTURI" ,(encode-and-join-uri-path iverilog-path))
|
||||
("VERILATORPOSTURI" ,(encode-and-join-uri-path verilator-path))
|
||||
("SAVECODEURI" ,(encode-and-join-uri-path savecode-path))
|
||||
("SAVEASURI" ,(encode-and-join-uri-path saveas-path))
|
||||
("HELPSTRING",
|
||||
(string-concatenate
|
||||
(insert-between
|
||||
@@ -510,14 +822,13 @@
|
||||
,(format "Icarus: ~a"
|
||||
(app-version (wrap-exe IVERILOG-EXE iverilog-wrap) "-V"))
|
||||
,(format "Verilator: ~a"
|
||||
(app-version (wrap-exe VERILATR-EXE verilator-wrap)))
|
||||
(app-version (wrap-exe VERILATOR-EXE verilator-wrap)))
|
||||
""
|
||||
"Rules:"
|
||||
"0. Don't fool around ;)"
|
||||
"1. The top module must be named 'testbench'."
|
||||
"2. The top module for the Verilator must have an input clock signal."
|
||||
"3. Code size should not exceed 10000 characters."
|
||||
"4. Code execution time no longer than 5 seconds.")
|
||||
"2. Code size should not exceed 10000 characters."
|
||||
"3. Code execution time no longer than 5 seconds.")
|
||||
"\\n"))))))
|
||||
(iverilog-metatop
|
||||
(call-with-input-file IVERILOG-METATOP-FILE get-string-all))
|
||||
@@ -547,9 +858,17 @@
|
||||
(<= (string-length code) max-code-size))
|
||||
code
|
||||
(substring code 0 max-code-size)))
|
||||
"")))
|
||||
""))
|
||||
|
||||
;; Request query
|
||||
(query (let ((q (uri-query (request-uri request))))
|
||||
(if q
|
||||
(map (lambda (qstr) (string-split q #\=))
|
||||
(string-split q #\;))
|
||||
'()))))
|
||||
|
||||
(logger LOG-VERBOSE "Request ~a:~a" (request-method request) path)
|
||||
(logger LOG-VERBOSE "Request query:~a" query)
|
||||
(logger LOG-DBG " stor:'~a' len:~a/~a"
|
||||
ref-stor-dir
|
||||
(request-content-length request)
|
||||
@@ -601,61 +920,64 @@
|
||||
;;
|
||||
((eq? 'POST (request-method request))
|
||||
(cond
|
||||
;; Run iverilog simulation
|
||||
((equal? path iverilog-path)
|
||||
(logger LOG-DBG "Request iverilog simulation")
|
||||
;; Run simulation
|
||||
((or (equal? path iverilog-path)
|
||||
(equal? path verilator-path))
|
||||
(let ((simulator
|
||||
(if (equal? path iverilog-path)
|
||||
'iverilog
|
||||
'verilator)))
|
||||
|
||||
(when ref-stor-dir
|
||||
(save-to-storage (path+ stor-base ref-stor-dir) code))
|
||||
(logger LOG-DBG "Request ~a simulation" (symbol->string simulator))
|
||||
(let-values
|
||||
(((log vcd)
|
||||
(exec-sim simulator
|
||||
(if sanitize (sanitize-verilog code) code)
|
||||
work-base
|
||||
TOP-MODULE
|
||||
#:metatop iverilog-metatop
|
||||
#:vvp-wrap vvp-wrap
|
||||
#:iverilog-wrap iverilog-wrap
|
||||
#:verilator-wrap verilator-wrap
|
||||
#:verilator-sim-wrap verilator-sim-wrap
|
||||
#:verilator-cpp verilator-cpp
|
||||
#:verilator-build-jobs verilator-build-jobs)))
|
||||
|
||||
(make-response
|
||||
(exec-sim 'iverilog
|
||||
(sanitize-verilog code)
|
||||
work-base
|
||||
TOP-MODULE
|
||||
#:metatop iverilog-metatop
|
||||
#:vvp-wrap vvp-wrap
|
||||
#:iverilog-wrap iverilog-wrap)
|
||||
#:content-type 'text/plain))
|
||||
|
||||
;; Run verilator simulation
|
||||
((equal? path verilator-path)
|
||||
(logger LOG-DBG "Request verilator simulation")
|
||||
|
||||
(when ref-stor-dir
|
||||
(save-to-storage (path+ stor-base ref-stor-dir) code))
|
||||
|
||||
(make-response
|
||||
(exec-sim 'verilator
|
||||
(sanitize-verilog code)
|
||||
work-base
|
||||
TOP-MODULE
|
||||
#:verilator-wrap verilator-wrap
|
||||
#:verilator-sim-wrap verilator-sim-wrap
|
||||
#:verilator-cpp verilator-cpp)
|
||||
#:content-type 'text/plain))
|
||||
(let ((canvas-width
|
||||
(let ((v (assoc "width" query)))
|
||||
(or (and v (string->number (cadr v)))
|
||||
DEFAULT-CANVAS-WIDTH))))
|
||||
(make-response
|
||||
(make-log-html log vcd canvas-width)
|
||||
#:content-type 'text/plain)))))
|
||||
|
||||
;; Save snippet
|
||||
((or (equal? path savecode-path)
|
||||
(equal? path saveas-path))
|
||||
(let ((saveas (equal? path saveas-path)))
|
||||
(logger LOG-DBG "Request code saving~a"
|
||||
(if saveas " as new snippet" ""))
|
||||
(let ((stor-dir
|
||||
(if (or saveas
|
||||
(not ref-stor-dir))
|
||||
((or (equal? path savecode-path))
|
||||
(logger LOG-DBG "Request code saving")
|
||||
(let ((old-code
|
||||
(if ref-stor-dir
|
||||
(read-from-storage (path+ stor-base ref-stor-dir))
|
||||
DEFAULT-CODE)))
|
||||
(if (equal? code old-code)
|
||||
;; If code is not changed do nothing
|
||||
(make-response
|
||||
(encode-and-join-uri-path
|
||||
(append root-path `(,ref-stor-dir)))
|
||||
#:content-type 'text/plain)
|
||||
;; New code save to new location
|
||||
(let ((stor-dir
|
||||
(basename
|
||||
(mkdtemp
|
||||
(path+
|
||||
stor-base
|
||||
(format "~a-XXXXXX"
|
||||
(current-time)))))
|
||||
ref-stor-dir)))
|
||||
(save-to-storage (path+ stor-base stor-dir) code)
|
||||
(make-response
|
||||
(encode-and-join-uri-path
|
||||
(append root-path `(,stor-dir)))
|
||||
#:content-type 'text/plain))))
|
||||
(if USE-TIME-IN-SAVE-URL
|
||||
(format "~a-XXXXXX" (current-time))
|
||||
"XXXXXX"))))))
|
||||
(save-to-storage (path+ stor-base stor-dir) code)
|
||||
(make-response
|
||||
(encode-and-join-uri-path
|
||||
(append root-path `(,stor-dir)))
|
||||
#:content-type 'text/plain)))))
|
||||
|
||||
;; Wrong POST request
|
||||
(else
|
||||
@@ -694,7 +1016,9 @@
|
||||
(-> " --vvp-wrap PATH Icarus Verilog interpreter wrapper.")
|
||||
(-> " --verilator-wrap PATH Verilator compiler wrapper.")
|
||||
(-> " --verilator-sim-wrap PATH Verilator simulation executable wrapper.")
|
||||
(-> " --verilator-build-jobs N Verilator parallel build.")
|
||||
(-> " --max-len LEN Set maximum code size in symbols. Default: 0 (infinite)")
|
||||
(-> " --dont-sanitize Do not sanitize verilog code (dangerous)")
|
||||
(-> " --work-base PATH Set work base path. Default: ./")
|
||||
(-> " --stor-base PATH Set snippets storage path. Default: ./")
|
||||
(-> " --log-level LEVEL Set log level from 0 (quiet) to 10 (verbose). Default: 1./")
|
||||
@@ -704,7 +1028,7 @@
|
||||
|
||||
(define (string-trim-if-string str)
|
||||
(if (string? str)
|
||||
(string-trim str)
|
||||
(string-trim-both str)
|
||||
str))
|
||||
|
||||
(define (main args)
|
||||
@@ -720,24 +1044,28 @@
|
||||
'(("iverilog-wrap") required)
|
||||
'(("verilator-wrap") required)
|
||||
'(("verilator-sim-wrap") required)
|
||||
'(("verilator-build-jobs") required)
|
||||
'(("max-len") required)
|
||||
'(("dont-sanitize") none)
|
||||
'(("work-base") required)
|
||||
'(("stor-base") required)
|
||||
'(("log-level") required)
|
||||
'(("help" #\h) none))))
|
||||
|
||||
(let ((addr (string-trim (or (option-get opts "addr") "127.0.0.1")))
|
||||
(port (string->number (string-trim (or (option-get opts "port") "8080"))))
|
||||
(host (string-trim (or (option-get opts "host") "http://127.0.0.1:8080")))
|
||||
(root (string-trim (or (option-get opts "root") "")))
|
||||
(let ((addr (string-trim-both (or (option-get opts "addr") "127.0.0.1")))
|
||||
(port (string->number (string-trim-both (or (option-get opts "port") "8080"))))
|
||||
(host (string-trim-both (or (option-get opts "host") "http://127.0.0.1:8080")))
|
||||
(root (string-trim-both (or (option-get opts "root") "")))
|
||||
(vvp-wrap (string-trim-if-string (option-get opts "vvp-wrap")))
|
||||
(iverilog-wrap (string-trim-if-string (option-get opts "iverilog-wrap")))
|
||||
(verilator-wrap (string-trim-if-string (option-get opts "verilator-wrap")))
|
||||
(verilator-sim-wrap (string-trim-if-string (option-get opts "verilator-sim-wrap")))
|
||||
(max-code-size (string->number (string-trim (or (option-get opts "max-len") "0"))))
|
||||
(work-base (string-trim (or (option-get opts "work-base") "./")))
|
||||
(stor-base (string-trim (or (option-get opts "stor-base") "./")))
|
||||
(log-level (string->number (string-trim (or (option-get opts "log-level") "1")))))
|
||||
(verilator-build-jobs (string->number (string-trim-both (or (option-get opts "verilator-build-jobs") "0"))))
|
||||
(max-code-size (string->number (string-trim-both (or (option-get opts "max-len") "0"))))
|
||||
(sanitize (not (option-get opts "dont-sanitize")))
|
||||
(work-base (string-trim-both (or (option-get opts "work-base") "./")))
|
||||
(stor-base (string-trim-both (or (option-get opts "stor-base") "./")))
|
||||
(log-level (string->number (string-trim-both (or (option-get opts "log-level") "1")))))
|
||||
|
||||
(cond
|
||||
(err
|
||||
@@ -757,7 +1085,9 @@
|
||||
(logger LOG-INFO "vvp wrapper: '~a'" vvp-wrap)
|
||||
(logger LOG-INFO "verilator compiler wrapper: '~a'" verilator-wrap)
|
||||
(logger LOG-INFO "verilator simulator wrapper: '~a'" verilator-sim-wrap)
|
||||
(logger LOG-INFO "verilator build jobs: ~a" verilator-build-jobs)
|
||||
(logger LOG-INFO "Max code size: ~a" max-code-size)
|
||||
(logger LOG-INFO "Sanitize code: ~a" sanitize)
|
||||
(logger LOG-INFO "Work base path: '~a'" work-base)
|
||||
(logger LOG-INFO "Storage base path: '~a'" stor-base)
|
||||
(logger LOG-INFO "Log level: '~a'" log-level)
|
||||
@@ -765,7 +1095,7 @@
|
||||
(run-server
|
||||
(make-page-handler host root INDEX-FILE
|
||||
work-base stor-base
|
||||
max-code-size
|
||||
max-code-size sanitize
|
||||
iverilog-wrap vvp-wrap
|
||||
verilator-wrap verilator-sim-wrap)
|
||||
verilator-wrap verilator-sim-wrap verilator-build-jobs)
|
||||
'http `(#:host ,addr #:port ,port)))))))
|
||||
|
||||
@@ -1,11 +1,11 @@
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module __@TOPMODULE@__;
|
||||
logic clock = 1'b0;
|
||||
initial forever #(5ns) clock = ~clock;
|
||||
@TOPMODULE@ @TOPMODULE@ (clock);
|
||||
@TOPMODULE@ @TOPMODULE@ ();
|
||||
|
||||
initial begin
|
||||
$dumpfile("@WORKDIR@/@TOPMODULE@.vcd");
|
||||
$dumpvars(0, @TOPMODULE@);
|
||||
$dumpvars(1, @TOPMODULE@);
|
||||
$dumplimit(100000);
|
||||
end
|
||||
endmodule
|
||||
|
||||
@@ -1,58 +1,43 @@
|
||||
#include "verilated.h"
|
||||
#include "verilated_vcd_c.h"
|
||||
#include "V@TOPMODULE@.h"
|
||||
|
||||
#include <cstdint>
|
||||
#include <verilated.h>
|
||||
#include <verilated_vcd_c.h>
|
||||
|
||||
#define DUMPFILE "@WORKDIR@/@TOPMODULE@.vcd"
|
||||
#define CLOCK_HALF_PERIOD 5000
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
VerilatedContext *ctx = new VerilatedContext;
|
||||
ctx->commandArgs(argc, argv);
|
||||
int main(int argc, char** argv, char**) {
|
||||
// Setup context, defaults, and parse command line
|
||||
Verilated::debug(0);
|
||||
const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
|
||||
contextp->traceEverOn(true);
|
||||
contextp->commandArgs(argc, argv);
|
||||
|
||||
/* Create model instance */
|
||||
V@TOPMODULE@ *top = new V@TOPMODULE@(ctx);
|
||||
// Construct the Verilated model, from Vtop.h generated from Verilating
|
||||
const std::unique_ptr<V@TOPMODULE@> topp{new V@TOPMODULE@{contextp.get()}};
|
||||
|
||||
#if (VM_TRACE == 1)
|
||||
VerilatedVcdC *vcd = new VerilatedVcdC;
|
||||
ctx->traceEverOn(true);
|
||||
top->trace(vcd, 99);
|
||||
topp->trace(vcd, 99);
|
||||
vcd->open(DUMPFILE);
|
||||
#endif
|
||||
|
||||
top->clock = 0;
|
||||
|
||||
/* ---- Evaluation loop ---- */
|
||||
for (;;) {
|
||||
/* Eval */
|
||||
top->eval();
|
||||
|
||||
/* Trace steady-state values */
|
||||
#if (VM_TRACE == 1)
|
||||
if (vcd) vcd->dump(ctx->time());
|
||||
#endif
|
||||
|
||||
/* Break exactly after calling $finish */
|
||||
if (ctx->gotFinish()) break;
|
||||
|
||||
/* Clock event */
|
||||
ctx->timeInc(CLOCK_HALF_PERIOD);
|
||||
top->clock = top->clock ? 0 : 1;
|
||||
// Simulate until $finish
|
||||
while (!contextp->gotFinish()) {
|
||||
// Evaluate model
|
||||
topp->eval();
|
||||
vcd->dump(contextp->time());
|
||||
// Advance time
|
||||
if (!topp->eventsPending()) break;
|
||||
contextp->time(topp->nextTimeSlot());
|
||||
}
|
||||
|
||||
top->final();
|
||||
printf("[%lu] Stop simulation\n", ctx->time());
|
||||
|
||||
#if (VM_TRACE == 1)
|
||||
if (vcd) {
|
||||
vcd->close();
|
||||
delete vcd;
|
||||
if (!contextp->gotFinish()) {
|
||||
VL_DEBUG_IF(VL_PRINTF("+ Exiting without $finish; no events left\n"););
|
||||
}
|
||||
#endif
|
||||
|
||||
delete top;
|
||||
delete ctx;
|
||||
// Execute 'final' processes
|
||||
topp->final();
|
||||
|
||||
// Print statistical summary report
|
||||
contextp->statsPrintSummary();
|
||||
vcd->close();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user